Range must be bounded by constant expressions

SystemVerilog
7

In reply to dave_59:

module wr_strb;
bit [15:0] Data = 'hFFFF;
bit [15:0] WDATA;

task strobe(int r);
WDATA[(4*r-1):0] = 'hx;
WDATA[15:(4*r)] =  Data[15:(4*r)];
$display("WDATA = %0h",WDATA);
endtask

initial
begin
strobe(2);
end
endmodule

Hi Dave,
i’m getting an error : “Range must be bounded by constant expression” for the above code.
If you have any solution for this please guide me.

thanks and regards,
Saroj Kumar Sahoo