Hi.
I’m trying to randomize with constrainted variable of Systemverilog as the below
class C;
rand int q[];
rand int wsize;
randc int index;
//int queue[$urandom_range(queue.size()-1)];
constraint select {
wsize inside {[0:10]};
q.size() == wsize;
index inside{[0:q.size()-1]};
}
endclass
module DA;
initial begin
C c;
c = new();
if(c.randomize())
$info("randc success");
else
$error("fail");
foreach(c.q[i])
$display("Randc:%0d", c.q[i]);
end
endmodule
But I keep faced fail, How do I success the randomization?
# vsim -voptargs=+acc=npr
# run -all
# testbench.sv(49): randomize() failed due to conflicts between the following constraints:
# testbench.sv(11): select { (wsize inside { [0:10] }); }
# testbench.sv(12): select { (q.size == wsize); }
# testbench.sv(13): select { (index inside { [0:(q.size - 1)] }); }
# Where:
# index = 663679149 /* random */
# Given:
# bit signed [31:0] q.size
# bit signed [31:0] wsize
# ** Note: (vsim-7130) Enabling enhanced debug (-solvefaildebug=2) may generate a more descriptive constraint contradiction report and -solvefaildebug testcase.
# ** Note: (vsim-7106) Use vsim option '-solvefailtestcase[=filename]' to generate a simplified testcase that will reproduce the failure.
# ** Warning: (vsim-7084) No solutions exist which satisfy the specified constraints; randomize() failed.
#
# Time: 0 ns Iteration: 0 Process: /DA/#INITIAL#22(#ublk#1153#22) File: testbench.sv Line: 49
# ** Error: fail