What are the common and good usage of pre_randomize() and post_randomize() in SystemVerilog?
I list out the some usages:
pre_randomize & post_randomize function can have several uses based on the application.
Here is the list of few usage of those functions.
Both functions can be overridden, and hence it can be possible to modify the randomization behavior with extended class
Turn on/off few random variables
Turn on/off few constraints
Assignments to other nonrandom variable, on which the randomization is dependent
Changing the weight of random variables, based on certain conditions
I got this much of information. if any one having extra knowledge please share me?
Calculating CRC or parity based on the random values generated. It can be done in the post_randomize()
Printing the random values immediately after randomization. It may help in debugging sometimes.
If the next values of random values are dependent on the previous random values, then, some kind of analysis can be done either in pre/post randomization methods to decide the next set of random numbers.
I would not use pre/post_randomize to turn on or off random variables. Some cases it’s too late because the random mode affects whether pre/post randomize gets called