Randomize always the same number with $urandom_range

SystemVerilog
1

Hi,

I am using the following code to generate a random number of 96 bits:

val = $urandom_range(0,96’hffffffffffffffffffffffff);

The problem is that it always return val=0xfff…ff

Can someone help me to find what’s wrong? Note that it works well with 32 bits words.

Thanks.

2

In reply to Paolo55:

$urandom_range() will only return a 32 bit unsigned integer. If you want to get a larger value, you will need to make several calls to the $urandom_range() function.


bit [95:0] val;

val[31:0]  = $urandom_range(32'hffff_ffff, 0);
val[63:32] = $urandom_range(32'hffff_ffff, 0);
val[95:64] = $urandom_range(32'hffff_ffff, 0);

or


val = {$urandom_range(32'hffff_ffff), $urandom_range(32'hffff_ffff), $urandom_range(32'hffff_ffff)};
3

In reply to cgales:
In reply to Paolo55:

The problem is the argument types and return value type of $urandom_range are 32-bit unsigned ints. I can’t explain the results you are getting, but the proper way to code this would be

randomize(val) with { val inside {[0,96’hffffffffffffffffffffffff]};};

4

Hi,

Thanks for your answers.
In fact I see now that my code was “correct”. It generates random 96 bits value but the distribution is not got. It was 50% 0x0 and 0xFF…F and 50% real random value.

In anyway I will use the solution of cgales to fix the distribution.

5

In reply to Paolo55:

you can use inline randomization

initial begin
obj = new();
repeat(10) begin
if(obj.randomize with { val inside {[0,96’hffffffffffffff];}};) begin
$display(“randomized value val = %0d”,val);
end
end
end

now even if you run for 10 different seeds you will see the same value.

6 
module tb;
  
  int a = $urandom_range(1,2);
  
  initial
     $display (a);
  
endmodule

why the above code displays 2 every time I compile+simulate it?

7

@dv_user
Try passing run-time argument ( Tool Specific ) to generate a random seed

8

every tool takes a different seed for new simulation, right? I even tried passing a different time as runtime option - but result stays same 2. did you tried simulating the code?

9

No, unless you pass the random seed run-time switch. Have you checked the seed used for each run ? Unless you pass the run-time switch, the seed remains the same

It’s possible that different seeds give the same output

Yes, I tested it on EDA. I do observe both values on each tool ( depending on seed )

10

Interesting. which tool did you use on EDA and what was the runtime argument? I can try the same at my end.

11

It is exactly doing what it should do because the randomization has to be repeatable. If the randomization would generate always differnt values you could never debug a failing testcase.

12

@dv_user, Check compile_run_options.html

13

Questa the command line is -sv_seed random. Whatever tool you use, it should echo the actual seed used so you can run a repeatable simulation.

# Sv_Seed = 2817203753