are you using $urandom and $random inside the class in SystemVerilog?
1 Like
In reply to anvesh dangeti:
I didn’t get your question exactly.
But, you can use both $random or $urandom inside SV class.
However, $urandom returns 32 bit unsigned value and $random returns 32 bit signed value.
my question is
we are able to you using “$urandom” and “$random” inside the class in SystemVerilog?
yes we can use
but it is un-constraint methods.
In reply to anvesh dangeti:
$urandom and $random are both functions returning 32-bit integral values that can be used in any integral expression. They cannot use be used in a constraint expression because they are not “pure” functions; they both modify a seed value which is not part of the return value.
$random should not be used with any SystemVerilog code.
In reply to dave_59:
Hi Dave,
Will you please help to explain more about below statement.
They cannot use be used in a constraint expression because they are not "pure" functions; they both modify a seed value which is not part of the return value.
Thanks!
In reply to harsh pandya:
See section 18.5.12 Functions in constraints in the IEEE 1800-2017 SystemVerilog LRM. Both these system function violate these restrictions.
In reply to dave_59:
Hi Dave,
I have gone through section you mentioned.
So, as per second rule says “( preserve no state information )”
And as you mentioned, $random/urandom modify seed value and not share/return modify seed value.
Hence, it violation of rules.
Is it correct understanding ?
Thanks!
I am not understanding what we are saying. please elaborate some better explanation.
In reply to anvesh dangeti:
Your question is very ambiguous. “Can you use $urandom in a class?” The answer to that is a generic yes. But could you write
class A;
$urandom;
endclass
The answer to that is no, it’s not valid syntax.
But you could write the following
class A;
int I = $urandom;
endclass
So you need to clarify what your concern is.
my concern is
class A;
int I = $urandom;
endclass
and my question is both $random and $urandom are used inside the class? or only $urandom is permitted?
In reply to anvesh dangeti:
As I said earlier, you can use $random or $urandom wherever an integral expression is allowed, irrespective of being inside a class or not. There are other restrictions, like side effects, that prevent certain functions and operators (e.g. ++,–) from being used in constraint expressions.
SystemVerilog introduces $urandom, which should replace the legacy use of Verilog’s $random. $urandom has the random stability features needed for testbench development that $random does not have. See section 18.14 Random stability in the IEEE 1800-2017 SystemVerilog LRM.
In reply to anvesh dangeti:
Generally you can use both.
As, SV is backwards compatible to verilog you can use $random.
However,$urandom is most recommended.
See, below example.
// Code your testbench here
// or browse Examples
class k;
int i = $random;
bit[31:0] j = $urandom;
endclass : k
module m;
k k1;
initial begin
k1 = new();
$display("i=%0d \nj=%0d",k1.i,k1.j);
end
endmodule : m
Results :-
# vsim -voptargs=+acc=npr
# run -all
# i=303379748
# j=3948585912
Thanks!
above code is working fine. Means both $random and $urandom are used inside the class?