Randomization

SystemVerilog
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1

What is the maximum range of randc variable most of the simulator can support? (Note:- some simulator support more)?

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Variables declared with the randc keyword are random-cyclic variables that cycle through all the values in a random permutation of their declared range. Random-cyclic variables can only be reg or enumerated types, and are limited to a maximum size of 16 bits, so the maximum range for any randc variable is 0 to 65535.
my doubt is randc having any range. or it is simulator based?

2

In reply to anvesh dangeti:

From LRM:
To reduce memory requirements, implementations may impose a limit on the maximum size of a randc variable, but it shall be no less than 8 bits.

3

but when I am randomizing a variable grater than 32 bit using randc it shows’ error :-
The object ‘vari’, which is 33 bits wide, was declared as randc. This is not
allowed; an object may not be declared randc if it is more than 32 bits in
width.
as per LRM:
To reduce memory requirements, implementations can impose a limit on the maximum size of a randc variable, but it should be no less than 8 bits.
less than 8 bit also working to randc variable
example:

class mypacket;
  randc bit [32:0] vari;
  endclass
 
module tb_top;
  mypacket pkt;
  initial begin
	pkt = new ();
	repeat(20)begin
	pkt.randomize ();
      $display ("Mode : %0d", pkt.vari);  
	end
  end
endmodule
4

In reply to anvesh dangeti:

The IEEE 1800-2017 SystemVerilog LRM is the only authoritative source for definition. The adherence to an IEEE standard is voluntary, and a tool may impose any limit they choose. But if they want to claim adherence to the standard, the only limit required is minimum of 8 bits.