In reply to withankitgarg:
It would help to show the complete context of where this repeat statement is located, as well as an example of the output you are getting versus what you expected.
Here is an example of a compete self-contained executable example for code snippet 2.)
module top;
initital
repeat(10) begin
int i ;
i = $urandom() ;
display(i);
end
endmodule
In the above case, the statement
i = $urandom(); gets executed each time through the repeat loop.
To do the same for the first code snippet would actually be illegal code and should have generated a compiler error. That is because declaration of i is, by default, a static variable and its initialization only happens once at time 0. The SystemVerilog LRM requires you to explicitly declare i as either static or automatic to make sure you are aware of the initent.
module top;
initial
repeat(10) begin
static int i = $urandom() ;
display(i);
end
endmodule