Randomization problem of enum in derived sequence item

UVM
1

hi

I made a base seq item like this and defined some enums and data items inside it. all data item are registered in factory with `uvm_field

class eth_rw extends uvm_sequence_item;
....

and i made another seq item derived from it and registered them

class ipv4_rw extends eth_rw;

typedef enum bit [3:0] {
 INVALID_IPV4                            =4'h0, //length is used instead
 IPV4_TYPE          =4'h4  
} ip_version_e; // user typedef

                                                               
  ip_version_e     ip_version;                                                                                       
  rand bit [3:0]     ihl;                                                                                           
  rand bit [7:0]     tos;            
......

in the test i use this to start the generation of ipv4_rw

  set_type_override_by_type(eth_rw::get_type(), ipv4_rw::get_type());

the problem is the generated ipv4_rw has all ip_version=0 . but the ihl and tos is real random value.
when I add the constraint

    constraint version_c {
      ip_version == 4'h4; 
     }

the questasim report error in simulation . i have no other constraint for this value.
i used questa 10.1d, is there anything wrong with my code or it’s a bug of the tool?

[RNDFLD] Randomization failed in uvm_do_with action

thanks

2

It appears that you are missing a “rand” in front of the ip_Version declaration.

3

thank you, i can’t believe how foolish i am.