Randomization only for part of data

SystemVerilog
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1

hi ,

i am new to system verilog randomization , can i know how to randomize the part of the data only , for example i have 8 bit data , in that 3bit is crc , which i do not want to randomize, like to calculate and replace that bit with it return value .

2

In reply to sekharece413:
There are a few different things you can do:

  1. You can constrain the crc bit with the function
constraint c_crc {data[7:5] == crc_func(data[4:0]); }
  1. After randomization, you can just replace the crc bits with the return value of the function. It will not matter if they were random before.
  2. You can add a constraint that leaves the 3 bits in their current state.
constraint c_crc {data[7:5] == const'(data[7:5]); }

I think 1) is your best option.