Randomization failure

SystemVerilog
,
1

Hi,

I am getting randomization fail, I don’t know why?

In testcase, I am randomizing config object class.

class my_test extends extends base_test;
    ............... 

    if(!hci_cfg.randomize() with {
                                   error_pkt[8] == 1;
                                 }

    ..............

enclass;

In hci_config the variable is declared as follows.

class hci_config extends uvm_object;
    .....................

    rand  bit [31:0] error_pkt;
    randc bit [63:0] error_field;

    constraint ERROR_PKT_ONE_HOT{
                                 $countones(error_pkt[11:0]) == 1;
                                 error_pkt[21:12]            > 0;
                                }

    constraint ERROR_PKT_FIELD  { 
                                  if(error_pkt[0]) {
                                      error_filed[13] == 1;
                                  }
                                }

    .....................
endclass

But in test if I give inline constraint like below, randomization will pass.

class my_test extends extends base_test;
    ............... 

    if(!hci_cfg.randomize() with {
                                   error_pkt[8]    == 1;
                                   error_pkt[7:0]  == 1;
                                   error_pkt[11:9] == 1;
                                 }

    ..............

enclass;

I am using questasim simulator.

Can anyone please explain why constraint is not applying properly?

Thanks in advance

2

In reply to basavaraj.ap:
Please refer Section 18.4.2 of IEEE Std 1800-2012.

18.4.2 Randc modifier

. . .

The semantics of random-cyclical variables requires that they be solved before other random variables. A set of constraints that includes both rand and randc variables shall be solved so that the randc variables are solved first, and this can sometimes cause randomize() to fail.

Also, the randc variable shall be 32 bits at max. I see it is 64-bit, please change it to 32 bits if possible.