Randomization failing

SystemVerilog
6

In reply to spat:

Declaring data_1 data_0 as logic in the interface gives a conflict in the top module saying:
** Error: (vsim-3053) top_dp.sv(30): Illegal inout port connection for “port ‘data_0’”.

Region: /top/DUT

** Error: (vsim-3053) top_dp.sv(30): Illegal inout port connection for “port ‘data_1’”.

Region: /top/DUT