In reply to Tudor Timi:
Thanks so much Tudor… Thats working now.
I have two more things to be discussed:
- After getting done with that, I came across another issue, pertaining to put methods from the generator, which I did solve but I yet haven’t understood the essence of the issue I was facing. So if you look into task generate_s() inside class test (highlighted by comment XXXXXXXXXXXXXXX & YYYYYYYYYYYYYYYY in the following), I was using two separate mailboxes mail and mail1 and to put the object sti of the packet. I was getting them in drivers and scoreboards as mail & mail1 respectively.
task generate_s(input integer iteration);
repeat(iteration)
begin
if(sti.randomize()) with {cs_0==1; we_0==1; cs_1==1; we_1==0; oe_1==0; }) // line 15
begin
$display(“********************”);
mail.put(sti); // XXXXXXXXXXXXXXX
mail1.put(sti); //YYYYYYYYYYYYYYYY
$display(“randomization successfull”);
end
else $display(“failed”);
end
endtask
The fatal error i used to get on doing run -a was again bad hanlde reference making the questa sim hang, whaich had to restarted! On debugging it, all I did now is just using one mail to put from test and get in scoreboard and driver. Basically got rid of mail1. Things work fine. Validated this by displaying the randomized values in all the 3 classes and they are same. Need to understand why using two mailboxes was a issue?
- I have this inout problem. the error I get is (highlighted byXXXXXXXXXX & YYYYYYYYYYYYYY in driver class )
** Error: (vsim-8220) driver_dp.sv(30): This or another usage of ‘intf.data_0’ inconsistent with ‘net’ object.
Region: /top_dp_sv_unit
** Error: (vsim-8220) driver_dp.sv(31): This or another usage of ‘intf.data_1’ inconsistent with ‘net’ object.
Region: /top_dp_sv_unit
Error loading design
data_1 & data_0 are the dual ports.
CODES*****
interface*
interface int_dp(input bit clk);
logic cs_0;
logic we_0;
logic oe_0;
logic cs_1;
logic we_1;
logic oe_1;
logic [11:0] addr_1;
logic [11:0] addr_0;
wire [7:0] data_0;
wire [7:0] data_1;
modport tb (output cs_0,cs_1,we_0,we_1,oe_0,oe_1,addr_1,addr_0,clk, data_1,data_0);
endinterface
TOP*
module top;
bit systemclk;
int_dp intf(systemclk); // interface instantiation
ram_dp_srw DUT(
.clk(systemclk), // dut instantiation
.cs_0(intf.cs_0),
.cs_1(intf.cs_1),
.we_0(intf.we_0),
.we_1(intf.we_1),
.oe_0(intf.oe_0),
.oe_1(intf.oe_1),
.address_0_in(intf.addr_0),
.address_1_in(intf.addr_1),
.data_0(intf.data_0),
.data_1(intf.data_1));
testcase testcase_0(intf); // program block instantiation
initial begin
#100000 $finish;
end
initial begin //clk generation
systemclk = 0;
forever
#5 systemclk = ~systemclk;
end
endmodule
Driver****
class driver;
packet sti;
virtual int_dp.tb intf;
mailbox #(packet) mail;
function new (virtual int_dp.tb intf, mailbox #(packet) mail);
this.intf = intf;
this.mail = mail;
endfunction
task drive(input integer iteration);
repeat(iteration)
begin
mail.get(sti);
$display(" packet at driver = %p", sti);
@(posedge (intf.clk));
begin
intf.cs_0 <= sti.cs_0;
intf.we_0 <= sti.we_0;
intf.oe_0 <= sti.oe_0;
intf.cs_1 <= sti.cs_1;
intf.we_1 <= sti.we_1;
intf.oe_1 <= sti.oe_1;
intf.addr_0 <= sti.addr_0;
intf.addr_1 <= sti.addr_1;
intf.data_0 <= sti.data_0; //XXXXXXXXXXXXXXXXXXXXXXX
intf.data_1 <= sti.data_1; //YYYYYYYYYYYYYYYYYYYYYYY
end
end
endtask
endclass
Would be extremely happy to have your inputs! Thanks in advance. I have been facing this inout issue since my verilog times.