Randomization control

SystemVerilog
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5

In reply to dave_59:

BTW, I just found a way to do this without using pre_randomize or extra variables. SystemVerilog has a const’(expression) cast which means treat the expression as a const variable.

class my_class;
  rand some_type_e field1;
  rand int field2;
  rand int field3;
 
  constraint keep {(field1 == KEEP) -> (field3 == const'(field3)); solve field1 before field3;}

endclass