Randomising a logic vector of more than 32 in System Verilog

SystemVerilog
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2

In reply to Mitu Raj:

The SystemVerilog LRM allows implementations to limit the number of bits of a random variable that can be cyclic with randc. As soon as you add constraints to that variable, it becomes extremely difficult to figure out when you’ve cycled through all possible solutions.

You can try this brute force method using post_randomize and a queue.

class Config ;
   rand vec_config pkt ;
   vec_config pkt_q[$];
 
   constraint pr_constr {
                         if (condition)  { pkt.pr [2 : 0] <= '1 ;};
                        }
   constraint un_constr {
                        unique {pkt, pkt_q};
                        }
  function void post_randomize();
     pkt_q.push_back(pkt);
  endfunction
endclass