Random Clock Generator

HI,

Could you let me know how to generate a random clk generator.
means it should have a random time difference between edges. can we do it using rand key words in classes?
I have tried in in Verilog using $random keyword like below.
module clk_gen;
int I = $random;
always #I; clk=~clk;
endmodule
Please suggest correct way of generating random clk .

In reply to muralidar:

You can try below code.

always begin
rand_val = $urandom_range(max,min); // you might see a glitch if the value is 0.
#rand_val clk =~ clk;
end

“rand/randc” keyword in class is used to declare variables which will get random values when obj.randomize() is called. variables which doesn’t have these keywords are not randomized when obj.randomize() is called.