Rand_mode confusion in LRM

SystemVerilog
,
1

Hi all ,


LRM 18.8 ::  The syntax for the rand_mode()  method is as follows:

task object[.random_variable]::rand_mode( bit on_off );
or
function int object.random_variable::rand_mode();

The object is any expression that yields the object handle in which the random variable is defined.
The random_variable is the name of the random variable to which the operation is applied. 


For unpacked array variables, random_variable can specify individual elements using the corresponding            
index. Omitting the index results in all the elements of the array being affected by the call."

The function form of rand_mode()  only accepts singular variables; thus, if the specified variable is an          
unpacked array, a single element shall be selected via its index

**I am confused with the last line in LRM .

It says I can’t call rand_mode( 0 ) on a random unpacked property .**

However when I try following code ::


class Main ;

  rand bit [1:0] A [2] ;

 endclass

 Main m ;

 initial begin

   m = new() ;

  if ( m.randomize() )
   begin
     $display("Success with %p",m);
   end
 else
    $display("Fails");

  m.A.rand_mode(0) ; // [a1] Legal ??

  if ( m.randomize() )
   begin
     $display("Success with %p",m);
   end
 else
    $display("Fails");
  
  m.A[1].rand_mode(1) ; // [a2] Legal ??

  if ( m.randomize() )
   begin
     $display("Success with %p",m);
   end
 else
    $display("Fails");

 end

I Observe that [a1] N [a2] both work !!

i.e 1 possible Output is ::

      **Success with '{A:'{'h3, 'h2}}
      Success with '{A:'{'h3, 'h2}}
      Success with '{A:'{'h3, 'h1}}**

[Q] Is my interpretation about the last line wrong OR are simulators violating the LRM ??

2

In reply to Have_A_Doubt:

Some simulator are violating or enhancing the LRM depending on your point of view.