Hi,
In my project there are two environment . I have to use one reg_block for each environment. Could someone help me out with example.
Problem: reg_block_1–>env1
reg_block_2—>env2
I have created a top reg_block which will instantiate reg_block_1 and reg_block_2
in Build function i have added top_map.add_submap(reg_block_1) & top_map.add_submap(reg_block_2).
Now in the env how should i need to connect reg_block_1 needs to run on one sequencer and reg_block_2 needs to run on other sequener.
is it possible to use same map for multiple interface?
Please help
Regards,
Mechanic
In reply to Mechanic:
As per my understanding ::
The moment you map the 2 sub-blocks to the same register map ( top_map ) ::
top_map.add_submap(reg_block_1 , offset1 ) ; top_map.add_submap(reg_block_2 , offset2 ) ;
the Sequencer associated with top_map would be used by default for Frontdoor access to registers within reg_block_1 and reg_block_2
Each register map corresponds to a physical interface
i.e Each interface would correspond to 1 register map which would be associated with 1 driver - sequencer pair .
You need to add another register map for reg_block2 . Then ::
top_map1.add_submap(reg_block_1 , offset1 ) ;
top_map2.add_submap(reg_block_2 , offset2 ) ;
Then you can call set_sequencer for top_map1 and top_map2 to map them to the respective sequencer as per your requirements .
In reply to MICRO_91:
Thanks for the reply.
which means there is no need of top_reg_block.
we need to instantianre two maps separately
correct me if i am wrong.
one more thing : how can we take care of two interfaces try to access the same register
there will be race condition ?could you please provide your inputs heres
Regards,
Mechanic
In reply to Mechanic:
You would need top_reg_block . An addition is to declare another register map within the top_reg_block .
// Your top_reg_block would look like ::
rand reg_block1 reg_block1_h ;
rand reg_block2 reg_block2_h ;
uvm_reg_map reg_map1 , reg_map2 ; // 2 register maps corresponding to 2 interfaces
// Within build()
(1) create reg_block1 and reg_block2 and then call their respective build()
(2) create reg_map1 and reg_map2
(3) reg_map1.add_submap(reg_block1_h , offset1 ) ;
reg_map2.add_submap(reg_block2_h , offset2 ) ;
Then within top_env / base_test which instantiates env1 and env2
// Within build_phase()
(1) create env1 , env2 and other sub-components
(2) create top_reg_block and call it's build() // Can be done in connect_phase() as well !!
// Within connect_phase() ::
// Map the sequencers ::
top_reg_block_h.reg_map1.set_sequencer( env1.agnt_h.seqr , env1.agnt_h.adaptr_h );
top_reg_block_h.reg_map2.set_sequencer( env2.agnt_h.seqr , env2.agnt_h.adaptr_h );
one more thing : how can we take care of two interfaces try to access the same register
I am not sure about this . I do observe that **uvm_reg has a semaphore ( maybe for the same reason to ensure that only 1 access is active at a time )
**
Also from Design perspective wouldn’t there would be some logic ( eg: priority mechanism ) to grant access to a shared register between 2 interfaces .
Maybe the moderators / senior members of the forum can guide us on parallel access scenario .