In reply to mitesh.patel:
In reply to rajesh.deshpande:
Hi Rajesh,
Thanks for the response.
I am confused with sentence “Mirrored value can get changed at run time inside DUT. Desired value is the value programmed or predicted by testbench.”.
As per my knowledge, mirrored value is not inside DUT, it is part of uvm_reg_field. Can you please elaborate more about this sentence.
Apart from that, based on your reply, desired value is something which we programmed and we expect that, design register should have it. while mirrored value is updated based on the bus transaction.
Now, question is, whenever bus transaction is completed, uvm_reg will call the do_predict() method, which will update desired and mirrored value both. so, why both needs to update? ideally, only mirrored value should be updated, because our expected/programmed/desired value should not dependent on bus transaction.
Please provide your input on the same.
Thanks and Regards,
Mitesh Patel
Hi Mitesh,
The answer lies in different access policies defined (e.g. RW, W1C, RO, WC)
By definition, desired value is function of testbench set value, mirrored value and access policy. For RW policy, desired value is same as testbench set value i.e. mirrored value is irrelevant whereas for RO policy desired value is same as mirrored value i.e. testbench set value is irrelevant.
Every bus transaction changes the mirrored value and desired value is function of mirrored value so it must change.
Hope this answers your doubt.
Regards
Rajesh Deshpande