In reply to chr_sue:
In reply to verif_learner:
The IP-XACT Standard under preparation does not have readwriteOnce etc.
But it is still only a data format and it does not itself create a UVM register model.
Cadence uses this format for the register description for the UVM RAL. And for sure they do not only support the 3 access tpes defined in the IP-XACT spec.
ok. some confusion here. let me try to clarify.
RTL is already available and it is not based on IP-XACT. It does support features like clear on read. I cant do the same thing because IP-XACT has no way to specify this. So, my RAL model will be out of sync with RTL register model.
Please note that, IP-XACT is not just a data format. It is a specification.
So, unless it has a way to specify a feature, the downstream vendors cannot implement it.
I hope I have clarified my point …