class wr_rd_seq extends uvm_sequence#(mem_seq_item);
task pre_body();
// raise objection if started as a root sequence
if(starting_phase != null)
starting_phase.raise_objection(this);
endtask
task body();
`uvm_do_with(req,wr_en==1);
`uvm_do_with(req,rd_en==1);
endtask
task post_body();
// drop objection if started as a root sequence
if(starting_phase != null)
starting_phase.drop_objection(this);
endtask
endclass
In reply to Subhra Bera:
Starting_phase is an object which should exist during the run_phase.
Your code shows the implementation of the objections in a sequence. But this is only one place where the objections can be implemented.
In reply to chr_sue:
“Actually it is stated that starting_phase number is only set automatically if the sequence is started as default sequence for a particular phase.
When the sequence is started explicitly,the starting_phase member is null. so the sequence will not raise or drop objection.”--------please explain the above. How the sequence will be started as default? Anyway we have to start the sequence explicitly. From run_phase of test we have set _sequence.start(m_sequencer)
_ .How default sequence is started as default sequence for a particular phase?
In reply to Subhra Bera:
- set default sequence on command line +uvm_set_default_sequence
The +uvm_set_default_sequence=,, plusarg allows the user to define a default sequence from the command line, using the typename of that sequence.
<sim command> +uvm_set_default_sequence=path.to.sequencer,main_phase,seq_type
- config the default sequence use uvm_config_db in the test
uvm_config_db #(uvm_sequence_base)::set(null, "top.agent.myseqr.main_phase","default_sequence", myseq);
or
uvm_config_db #(uvm_object_wrapper)::set(null, "top.agent.myseqr.main_phase", "default_sequence", myseq_type::type_id::get());
In reply to Lina.Lin:
If we start the sequence as default then what will be there in run phase of test? “sequence.start(m_sequencer)”------is it will be there also? Or the run phase of test class will be empty?