Dear Dave,
I have tried the following code in Synopsys VCS compiler and could see race situation :
module test ;
reg [1:0]y;
initial
begin
#5 y <= 2;
end
initial
begin
y <= #5 3;
end
initial
#5 $strobe(“Value of y =%d”,y) ;
endmodule
Observation : y takes 3 or 2 as per the order of simulation .