Hi,
Could you please clarify my below doubts.
Thanks in advance.
LRM says “Together with clocking blocks, the program construct provides for race-free interaction between the design and the testbench, and enables cycle and transaction level abstractions”
My question is why its necessary to use the “clocking block along with program block” to avoid the race condition. It seems me to
- Clocking block with module can avoid race condition between design and testbench instead of using cb with program.
2)For RTL behavioral simulation program block can avoid the race condition even without using clocking block.
Please correct me if my understanding is wrong ??
My other question is from below paragraph does only non-blocking assignments sufficient to avoid the race condition ? if not could you please give me example where even there could be race condition exist even while using non blocking assignment.
“For Verilog-2001 designs and testbenches, applying stimulus on the active clock edge required that all stimulus be applied using nonblocking assignments to avoid race conditions with the registered logic of the design. In effect, applying stimulus using nonblocking assignments on the active clock edge mimicked the behavior of a 0-delay RTL register transfer from testbench to design.” By Clifford E. Cummings http://www.sunburst-design.com/papers/CummingsSNUG2006Boston_SystemVerilog_Events.pdf".
My other question is from below paragraph how “clock can propagates to some DUT inputs before the TB stimulus, but is a little later to other inputs” in behavioral RTL simulation.
[Page 92 Chapter 4:by Chris spear SystemVerilog for Verification]
“If the testbench drives the DUT at the clock edge, there could be race conditions. What if the clock propagates to some DUT inputs before the TB stimulus, but is a little later to other inputs? From the outside, the clock edges all arrive at the same simulation time, but in the design, some inputs get the value driven during the last cycle, whereas other inputs get values from the current cycle.”
I am using Questa sim and I want to induce race condition for learning sake and I drived the d input to DFF from testbench using blocking assignment even then I am not getting any race.
Could you please give me examples(both driving with blocking and non blocking) where there could be race between design and testbench while using module for testbench without using clocking block.
module DFF(
input d,
input clk,
input rst,
output reg q,
output reg qb
);
always @(posedge clk or negedge rst)
begin
if (~rst) begin
q <=0;
qb <=1;
end
else begin
q <= d;
qb <= ~d;
end
end
endmodule
module DFF_T();
parameter CYCLE = 10;
reg d=0;
reg clk;
reg rst;
wire q;
wire qb;
DFF DFF_Inst(.d(d), .clk(clk), .rst(rst), .q(q), .qb(qb));
initial begin
clk=0;
forever #(CYCLE/2) clk = ~clk;
end
initial begin
rst=1;
rst= 0;
#4 rst=1;
end
always @(posedge clk)
begin
d=~d;
$display("time:%t, d = %d >> Q is %d",$time,d,q);
end
endmodule
Thanks,
Gagan