Question regarding the sampling values

SystemVerilog
,
5

In reply to sa5691:
Before answering the specific questions, let me review important related points that can clarify some of your concerns:

  1. What is an event? 1800’2017: Every change in state of a net or variable in the system description being simulated is considered an update event.
  2. Processes are sensitive to update events. Examples of processes include, but are not limited to, primitives; initial, always, always_comb, always_latch, and always_ff procedures; continuous assignments; asynchronous tasks; and procedural assignment
    statements
  3. **sensitivity:**Processes are sensitive to update events. When an update event is executed, all the processes that are sensitive to that event are considered for evaluation in an arbitrary order. The evaluation of a process is also an event, known as an evaluation event.
  4. 1800’2017 9.4: Procedural timing controls: Time control statements are the # expression and @ expression constructs.
    …The first type is a delay control, in which an expression specifies the time duration between initially encountering the statement and when the statement actually executes.
    …The second type of timing control is the event expression, which allows statement execution to be delayed until the occurrence of some simulation event occurring in a procedure executing concurrently with this procedure.
    …Simulation
    time can advance by one of the following three methods:
    — A delay control, which is introduced by the symbol #
    — An event control, which is introduced by the symbol @
    — The wait statement, which operates like a combination of the event control and the while loop.

delay_control ::=
# delay_value
| # ( mintypmax_expression )
event_control ::=
@ hierarchical_event_identifier
| @ ( event_expression )
| @*
| @ (*)
| @ ps_or_hierarchical_sequence_identifier
event_expression31 ::=
[ edge_identifier ] expression [ iff expression ]
| sequence_instance [ iff expression ]
| event_expression or event_expression
| event_expression , event_expression
| ( event_expression )
procedural_timing_control ::=
delay_control
| event_control
| cycle_delay
...
wait_statement ::=
wait ( expression ) statement_or_null
| wait fork ;
| wait_order ( hierarchical_identifier { , hierarchical_identifier } ) action_block
edge_identifier ::= posedge | negedge | edge

Back to your questions:
There is a big difference between “what you can possibly do” and what you can safely do. You can drive a car on the wrong side of the road, but that there may be severe consequences in doing so. Keeping this in mind.


$rose:  Syntax: $rose(expr [,clk_evnt])
// You can write 
always @($rose(a, @(posedge clk)) ... // the rose of a is an event 
// The process will wake up at every rose.  Ok to do if this is what you want. 
// Definitely NOT OK for RTL designs, but OK for testbenches. 
// I don't believe that this type of structure is used often, and I personally prefer to 
// stick to traditional approaches, like 
always @(posedge clk) begin 
   if($rose(a) ... // the clock is inferred here. 

// 1800'2017 9.2.2.1 General purpose always procedure
/* If an always procedure has no control for simulation time to
advance, it will create a simulation deadlock condition.
The following code, for example, creates a zero-delay infinite loop: */ 
always areg = ~areg;

always $rose(a) // Illegal because of no clocks
always $rose(a, @(posedge clk)) // creates a zero-delay infinite loop
// the result of the $rose is a value, true or false. 
//-------------------
a_toggle : assert property (@(posedge clk) ##1 $changed(a));
a_toggle : assert property (@(posedge clk) 1 -> ##1 $changed(a)); // BAD practice
// The use of true as antecedent is meaningless and adds nothing, unless 
// you are in a debugging mode and just want to examine the consequent

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact http://cvcblr.com/home.html
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
…

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