In reply to ben@SystemVerilog.us:
Thank you Ben.
I am still little confused on $rose(a); and @(posedge a);
Like you said, both will detect if value changes from “0/x/z” to “1”
I was wondering if it is possible to use’m interchangeably ?
always @(posedge a)
always $(rose a)
property @(posedge a)
property $(rose a)
Or it is the rule to use only events while using always and properties, and why is that rule?
Also can you please throw your inputs on this.
logic a;
If “a” needs to toggle every clock cycle - i.e.
1 0 1 0 1 0 1 0
Which one is correct assertion to check? from below two options?
a_toggle : assert property (@(posedge clk) ##1 $changed(a));
a_toggle : assert property (@(posedge clk) 1 -> ##1 $changed(a));
Thank you,
Mega