Question regarding the sampling values

SystemVerilog
,
2

In reply to megamind:

  1. 1800’21017 states: $rose returns true (1’b1) if the LSB of the expression changed __to 1. Otherwise, it returns false (1’b0).
    Thus, X to 1 is a rose.
  2. @(posedge a); 1800’2017 9.4.2 Event control
  3. A negedge shall be detected on the transition from 1 to x, z, or 0, and from x or z to 0
    — A posedge shall be detected on the transition from 0 to x, z, or 1, and from x or z to 1
  4. $stable(a) 1800’2017
    $stable returns true (1’b1) if the value of the expression did not change. Otherwise, it returns false (1’b0). Thus, X to X is a no change
  5. $past returns the sampled value of expression1 in a particular time step strictly prior to the one in which $past is evaluated (see 16.5.1 for the definition of sampling in past clock ticks).
    Thus, if past was X, $past returns XX.
    If 1st clock (i.e., no past exists). it is the default sampled value of a static variable is the value assigned in its declaration, or, in the eabsence of such an assignment, it is the default (or uninitialized) value of the corresponding type

Sample code


 module m; 
    logic a, b;
    bit clk; 
    initial forever #10 clk = !clk;
    default clocking @(posedge clk); endclocking
    initial begin  
      $display("1  %t  $sampled(a} = %b", $realtime, $sampled(a));
      $display("1  %t a= %b", $realtime, a);
      $display("1  %t $rose(a)= %b", $realtime, $rose(a));
      $display("1  %t $stable(a)= %b", $realtime, $stable(a));
  
      @(posedge clk) a <= 1'b1; 
      $display("2  %t  $sampled(a} = %b", $realtime, $sampled(a));
      $display("2  %t a= %b", $realtime, a);     
      $display("2  %t $rose(a)= %b", $realtime, $rose(a));
      $display("2  %t $stable(a)= %b", $realtime, $stable(a));
      #1 $display("2 #1  %t a= %b", $realtime, a);

  
      @(posedge clk) a <= 1'b0;
      $display("3  %t  $sampled(a} = %b", $realtime, $sampled(a));
      $display("3  %t a= %b", $realtime, a);
      $display("3  %t $rose(a)= %b", $realtime, $rose(a));
      $display("%t $stable(a)= %b", $realtime, $stable(a));
  
      @(posedge clk) a <= 1'b1;
      $display("4  %t a= %b", $realtime, a);
      $display("4  %t  $sampled(a} = %b", $realtime, $sampled(a));
      $display("4  %t $rose(a)= %b", $realtime, $rose(a));
      $display("4  %t $stable(a)= %b", $realtime, $stable(a));
  
      @(posedge clk) a <= 1'b1; 
      $display("5  %t a= %b", $realtime, a);
      $display("5  %t  $sampled(a} = %b", $realtime, $sampled(a));
      $display("5  %t $rose(a)= %b", $realtime, $rose(a));
      $display("5  %t $stable(a)= %b", $realtime, $stable(a));

      @(posedge clk) a <= 1'b1; 
      $display("6  %t a= %b", $realtime, a);
      $display("6  %t  $sampled(a} = %b", $realtime, $sampled(a));
      $display("6  %t $rose(a)= %b", $realtime, $rose(a));
      $display("6  %t $stable(a)= %b", $realtime, $stable(a));

      @(posedge clk) a <= 1'b0;
      $finish;
    end
  endmodule
  
  # KERNEL: 1                     0  $sampled(a} = x
# KERNEL: 1                     0 a= x
# KERNEL: 1                     0 $rose(a)= 0
# KERNEL: 1                     0 $stable(a)= 1
# KERNEL: 2                    10  $sampled(a} = x
# KERNEL: 2                    10 a= x
# KERNEL: 2                    10 $rose(a)= 0
# KERNEL: 2                    10 $stable(a)= 1
# KERNEL: 2 #1                    11 a= 1
# KERNEL: 3                    30  $sampled(a} = 1
# KERNEL: 3                    30 a= 1
# KERNEL: 3                    30 $rose(a)= 1
# KERNEL:                   30 $stable(a)= 0
# KERNEL: 4                    50 a= 0
# KERNEL: 4                    50  $sampled(a} = 0
# KERNEL: 4                    50 $rose(a)= 0
# KERNEL: 4                    50 $stable(a)= 0
# KERNEL: 5                    70 a= 1
# KERNEL: 5                    70  $sampled(a} = 1
# KERNEL: 5                    70 $rose(a)= 1
# KERNEL: 5                    70 $stable(a)= 0
# KERNEL: 6                    90 a= 1
# KERNEL: 6                    90  $sampled(a} = 1
# KERNEL: 6                    90 $rose(a)= 0
# KERNEL: 6                    90 $stable(a)= 1

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact http://cvcblr.com/home.html
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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