In reply to ben@SystemVerilog.us:
Thanks Ben for the clarification on the “->” and “=” operator.
1.In the image the Sop is rising exactly at the posedge clk so the assertion will active from the next clock similarly for write and read .
Since assertions are evaluated in the pre-poned region
As per my understanding if i use → operator then the 2nd read and 3rd write and EOP must happen simultaneously.
please correct me if i am wrong.
2.I know that intersect is similar to and but both the sequences must be of same length.
If there are multiple intersect as mentioned above i got confused How it behaves. could you please help me out.
Thanks in advance