Question on posedge reset

SystemVerilog
1 
module exp;
  logic reset;
  task wait_reset();
   // @(posedge reset);
    $display("reset became high");
    @(negedge reset);
    $display("reset became low");
endtask
  initial begin
    reset = 1'b1;
    #1 reset = 1'b0;
   
  end
  initial begin
    $display("in the second initial block");
    wait_reset();
    $display("after reset the second initial block");
  end
endmodule

Hello,
I have system verilog code given above. It runs correctly and gives following output-

“Compiler version Q-2020.03-SP1-1; Runtime version Q-2020.03-SP1-1; Apr 15 08:36 2022
in the second initial block
reset became high
reset became low
after reset the second initial block”

However, if I remove the comment of // @(posedge reset) statement, and run the code,

it displays only “in the second initial block”
It does not seem to detect the posedge of reset and waits for it.
Now reset is initially x and then goes to 1 at time t = 0. Why is this transition not taken as posedge of reset?

Can someone help me to understand this behavior?
regards,
-sunil

2

In reply to puranik.sunil@tcs.com:

When removing the commented code, you have a race condition. You don’t know whether the
reset = 1’b1; or
@(negedge reset); executes first.

You should never write code that depends on seeing a posedge or negedge at time 0.