Question on net declaration

SystemVerilog
1

Hi,
I have a question on net declaration as follows :
If I declare a wire with following declaration,

wire integer x; or declare a port with inout wire integer y , I am getting syntax error with VCS simulator. Now the System verilog LRM gives following format for net declaration:

net_declaration12 ::= // from A.2.1.3
net_type [ drive_strength | charge_strength ] [ vectored | scalared ]
data_type_or_implicit [ delay3 ] list_of_net_decl_assignments ;

Now according to LRM, net_type can be supply0 | supply1 | tri | triand | trior | trireg | tri0 | tri1 | uwire | wire | wand | wor
and the data_type_or_implicit can be : data_type | implicit_data_type.
The data_type ::= integer_vector_type [ signing ] { packed_dimension }
| integer_atom_type [ signing ]
| non_integer_type
| struct_union [ packed [ signing ] ] { struct_union_member { struct_union_member } }
{ packed_dimension }13
| enum [ enum_base_type ] { enum_name_declaration { , enum_name_declaration } }
{ packed_dimension }
| string
| chandle
| virtual [ interface ] interface_identifier [ parameter_value_assignment ] [ . modport_identifier ]
| [ class_scope | package_scope ] type_identifier { packed_dimension }
| class_type
| event
| ps_covergroup_identifier
| type_reference14

Implicit_data_type ::= [ signing ] { packed_dimension }

Now based on above, it I write

wire integer x, it should be syntactically correct, since

wire is a legal net_type and integer is legal data_type.

Can someone explain if my understanding is correct and why should I get error for above declaration.

Also can someone explain when we need to use reference type when declaring module ports? What is the significance of reference keyword for module ports?

Thanks,
-sunil

2

In reply to puranik.sunil@tcs.com:

You are correct it should be legal. You need to contact your vendor to find out why it is producing an error.

A reference port work analogous to passing an argument of a task/function by reference. Instead of trying to make an assignment to a variable through a port, you are passing a reference to the variable that is connected to the port. In this way you are sharing a variable between two connected modules.

3

Thanks Dave for immediate reply.
rgs,
-sunil

4

In reply to dave_59:

In reply to puranik.sunil@tcs.com:
A reference port work analogous to passing an argument of a task/function by reference. Instead of trying to make an assignment to a variable through a port, you are passing a reference to the variable that is connected to the port. In this way you are sharing a variable between two connected modules.

Dave, i did not understand it, could you explain it?

5

In reply to prashant.kaushik:

I would avoid using this construct. It is really not necessary.