Question on Inheritance in SV

SystemVerilog
,
7

In reply to saurabh_3:

I update your code to have d3 as static, d4 as non-static and pass them to new(a,b). The sim result show display message as below. Not sure why you get 0 for both cases.

ZAM: static a_val: 6 non-static b_val:0


module top;
class C;                                                 
   int c1 = 1;
   int c2 = 1;
   int c3 = 1;
 
  function new(int a, int b);
    $display("ZAM: static a_val: %0d non-static b_val:%0d",a,b); // always getting display as 0
   c2 = 2;
   c3 = a;
endfunction
endclass
 
class D extends C;
   int d1 = 4;
   int d2 = c2;
   static int d3 = 6;
          int d4 = 6;
function new;
  super.new(d3,d4);
endfunction
endclass

D d1;
initial  begin
  d1=new();
end
endmodule