Question about un-named block

SystemVerilog
1

Can i access a variable which is inside un-named block?

 
 always_comb begin
   begin:a1
     static int i;
     i = 10;
   end
 end
initial begin
 $display("%d", a1.i);
end

I was expecting this to not work because the original begin-end is un-named. Can someone explain the reason why this variable can be accessible?

2

Identifiers defined inside an unnamed block should not be visible outside that block according to the LRM. Consider a tool bug if you are allowed to access it. Unfortunately, some tool bugs become undocumented features of the language that all tools implement. This may be one of the cases where the unnamed block is stripped away for being superfluous. If you add a variable declaration inside that unnamed block, then the a1 block becomes inaccessible.

3

In reply to dave_59:

Apparently this feature is documented:

An unnamed block creates a new hierarchy scope only if it directly contains a block item declaration, such as a variable declaration or a type declaration.

This peculiarity arose because Verilog 1364 did not allow declarations in unnamed blocks.

4

In reply to dave_59:

Thanks Dave, In the above code i am able to access variable “i” using a.i notation. So looks like as long as we are not having any variable declared inside un-named block named sub-blocks can be accessed directly