Hi all:
I have a question about adding System verilog assertions in Verilog design file.
During compilation, in order to collect assertion msg, I have to add -sv command, but as the original dut file is written by pure verilog, and there are some System verilog keywords in it (etc. reg [63:0]logic ). So the -sv compilation failed. If I use the**begin_keywords "1800-2005"** **end_keywords** , then the added assertions can’t be properly compiled…
My question is : if there is any solution by not changing the conflict definition in design file ?
If you are adding assertions directly in the design file, then you might as well change the variable called logic to something else, and rename the file to have a *.sv extension. Do not use the -sv switch. That way files with the *.v extension will still be treated as pure old Verilog. Note that most synthesis tools support SystemVerilog for design now.
If you really do not want to modify the design file, the you can use the bind construct to add assertions to the design. The assertion is put into a SystemVerilog module by itself and the bind construct instantiates the module into the design without modifying the original Verilog module. Just do a search for “bind SystemVerilog assertion” for examples.
Dave is correct. If you’re are allowed to touch the design and add assertions then you should be allowed to change the variable called logic. FWIW, logic is a very weird name for a variable!
I add an example of the use of the bind from our SystemVerilog Assertion Handbook (3rd Edition) in http://systemverilog.us/bind_example.tar It includes the following 3 files: counter.sv counter_props.sv counter_tb.sv