In reply to SATYA369:
Hi,
I’m working on RAL and I’ve got some doubts regarding RAL,can anyone help me with these?
1.give me a scenario in which only the mirrored value gets updated and the desired should not get updated.Actually I tried like this.
I used Backdoor write and Backdoor read so that there will be no data in the interface and since predictor converts the data in the interface in to reg_transaction,now it cannot update desired value.But what’s happening is both the desired and mirrored value are updating.
2.I’m using randomize() method to randomize a field,and while configuring I gave the argument .is_rand(1).But it’s not randomizing.Is there something else that I need to do?
3.By using get() - we can get the desired_value of the register
get_mirrored_value() - we can get the mirrored_value of the register
but how to get the value_field? Is there any scenario in which I can desired_value,mirrored_value,value fields each a different value?
Thank you
SATYA
I’d recommend to check this link UVM Tutorial for Candy Lovers – 16. Register Access Methods – ClueLogic to understand better about the different attributes the uvm_reg and uvm_reg_field has.
1- For example imagine you have a RO or status register to which you are doing some checker or predictor using predict() method to set the mirror value, at some point you’ll need to do rg.mirror() to do some comparison between what you predicted and what the DUT actually has then after the check the 3 values (value, desired, and mirrored should be in sync)
2- Not sure what you mean by not randomising, can you show an example, I’d expect the .value member to be randomised according to its constraints
3- To get the value which is used for FCOV and randomisation you could do rg.field.value
Also the case of modelling status register is a case in which these 3 values can differ.
HTH,
-R