module top;
bit a;
initial
uvm_config_db#(bit)::set(uvm_root::get(),"","CONFIG_1",a);
endmodule
And doing a get of the variable in sequence (Class)
class sequence extends uvm_sequence;
bit a
virtual task body();
if(! uvm_config_db #(bit)::get(null, "", "CONFIG_1", a))
`uvm_fatal(get_type_name(), "Can't Get A")
endtask
endclass
I am not getting any fatal error here, at the same time the actual value of “a” is not got in the sequence and always shows as ‘0’. Is there any limitation here in passing variable between Module->class and only interfaces can be passed?
you can pass the variable to the sequencer, then in you sequence call get_sequencer() to retrieve the sequencer handle to probe the value.
Alternative, put the variable into a config object, use uvm_event_pool to get a global event, call uvm_event::trigger(config_obj) to pass the object into the event, then in your sequence get the global event call uvm_evnet::wait_trigger_data(config_obj) to retrieve the object.