Put a transaction into analysis fifo

UVM
,
1

Hi,I want to put a transaction in analysis fifo but i am not able to put it.I have a class and it has the

uvm_tlm_analysis_fifo#(spi_uvc_transaction) seq_item_fifo

and this fifo is not connected to any other port or export. and i tried using this both methods,

seq_item_fifo.write(trans_h); or seq_item_fifo.put(trans_h);

but it is not working.

Thanks.

2

In reply to m_v:

What do you mean by “not working”? Are you getting a compilation error? Run-time error? Are you not seeing the results you expect? How are you testing?

It would help to show a minimal compete example of what you are trying to accomplish.

3

In reply to cgales:

OK.
There is no error but also i am not able to put the data in analysis fifo.
I am adding some part of the code.

code:-


class spi_slave_sequencer extends uvm_sequencer#(spi_transaction);
   
  `uvm_component_utils(spi_slave_sequencer);

  uvm_tlm_analysis_fifo#(spi_transaction) seq_item_fifo;

  spi_transaction spi_trans_h;

  extern function new(string name = "spi_slave_sequencer",uvm_component parent);

  extern function void connect_phase(uvm_phase phase);

  extern task run_phase(uvm_phase phase);
  
endclass : spi_slave_sequencer

  function spi_slave_sequencer::new(string name = "spi_slave_sequencer",uvm_component parent);
    super.new(name,parent);
    ..............
    /** A analysis fifo to store the transaction*/
    seq_item_fifo = new("seq_item_fifo",this);
  endfunction : new


  function void spi_slave_sequencer::connect_phase(uvm_phase phase);
    super.connect_phase(phase);
  endfunction : connect_phase

  task spi_slave_sequencer::run_phase(uvm_phase phase);
    .........
      //seq_item_fifo.write(spi_trans_h);
      seq_item_fifo.put(spi_trans_h);
      $display("fifo size = %0d",seq_item_fifo.size());
    ...........     
  endtask :run_phase
4

In reply to m_v:

You should never extend the uvm_sequencer class. The reason for this is that the run_phase() in the base uvm_sequencer is required to execute for proper functionality.

You should use a typedef:


typedef uvm_sequencer#(spi_transaction) spi_slave_sequencer;
5

In reply to cgales:

Hi, can you elaborate how it will effect the functionality of the sequencer.

Thank you.

6

In reply to m_v:

Using TLM connectios has to consider some restrictions. You can pass a transaction from a port to an export. The uvm_tlm_analysis_fifo itself has an export. But the question si what do you want to do with the content of your analysis fifo in your sequencer?
Could you pleas explain?

7

In reply to chr_sue:

Hi,
In this project i wanted to make a reactive agent and i have created a memory component in slave agent so i wanted to update that memory component through the slave sequencer via write and read API methods because we can not take memory in driver, monitor and sequence.

Slave sequencer has 2 fifo one fifo stores the write and read transactions and other stores the read transactions only. so my slave monitor is sampling the write or read transaction and put it in a fifo which is in the slave sequencer and in the sequencer only i am updating that memory component using API methods, and in another fifo i am putting only read transactions as per the read address with read data so i can retrieve it in the slave sequence.

Thanks.

8

In reply to m_v:

I’m not sure if I understandf your approach correctly.
How does the API work? Does it have really no pinlevel interface? And the usage of an anylysis fifo might not be te right one. You could consider your memory componet like driver and use the sam interface as the driver is using.