In VHDL, I can use an assert statement with a severity “note” to put a mark in the waveform viewer when interesting events take place. I am now doing straight Verilog/System Verilog. I would sure like to be able to do the same thing from verilog, but I cannot find anything in the Questa/Modelsim documentation that discusses this and the verilog assert statements don’t do it.
Does anyone know how to do this?
SystemVerilog has $info/$warning/$error/$fatal which are similar to the report severity statements in VHDL. In Questa, you need to use the vsim -msgmode switch to record the messages in the waveform database. Not only will you get a mark in the waveform viewer, but you also get a hyperlink to the source code where the message was emitted.
If you use the UVM for nothing else, I strongly suggest you learn and use the 4 macros uvm_info, uvm_warning, uvm_error, and uvm_fatal. This gives you tremendous power to filter messages from the simulation command line, as well as promote or demote messages severities, set breakpoints, and write report catchers to perform actions when certain messages are reported.
Dave