Hello,
I am dealing with a scenario where my UVC is in slave mode. Whenever DUT initiate a read transaction(addr and read_en), UVC just need to drive a random data(read_data). I am user in this scenario I need to use uvm_push_sequencer and uvm_push_driver so that driver can ask for the sequence to sequencer whenever he monitors a read_en. Am I correct?
If so can someone let me know how the sequencer selects a particular sequence, randomize it(or value from user(test_case) and provide it to driver
I am aware of the connection between push_driver and push_sequencer. But I dont know which method is used by req_export of driver and req_port of sequencer for this communication
Please help
In reply to rexjohn4u:
I do not really understand your problem. To clarify: the DUT will never initate something on its own. It has to be stimulated through some pin connections. The corresponding pin wiggles should be generated by a corresponding transaction, delivered to a uvm_driver.
BTW a READ in my eyes means a driver is providing an address and may be some control signals to the DUT. And the DUT respons with a data on the rd-line. Correct also in your case? A UVC should never generate a data item in case of a read.
Hi chr_sue,
As i mentioned before my UVC is the slave. DUT is the master in this case. Read request is generated by DUT. Slave responds with a read data.
What you assumed/solved is the reverse case where UVC is master and DUT is slave. I am aware of what to do in this case.
We are deviating from the topic!! Can someone respond to my actual query
Thanks Dave. This works fine for my scenario
Dave,
I have one more query.
If I am planning to implement a UVC, those memory/register instances mentioned in the uvc seq will be unknown for me right? This memory/register instances will come in to picture when we have the entire TB is available. So it this a good practice to add those in the UVC seq?
In reply to rexjohn4u:
Don’t know which memory/registers you are referring to. Perhaps you should start a new question and explain further.
Dave,
I am referring in same context.
Sequences/Slave | Verification Academy you have shared, inside the sequence you are fetching read data from a memory. But let say in my case I will be needing reg_model/memory_model read data here. In that case this sequence/base sequence must have the handle to this reg_model/mem_model which is an unknown part to my UVC right. Only a tb who is going to use this UVC can know about the source of this read_data.
How can I handle this scenario?