Hi,
Following property shows elab issue: Property operator usage is not allowed in sequence context.
What is wrong with it? How should it be written to resolve elab issue?
(sig1==0) |-> ##7 (($stable(sig2)) until (sig1 [->1]));
When I replace “until” with “throughout” it doesn’t show any issue.
The issue you’re encountering is related to the use of the “until” operator within the sequence context in SystemVerilog assertions. The “until” operator is not allowed directly in a sequence. However, the “throughout” operator can be used in a sequence context.
When using the “until” operator, it is typically used in a property or an assertion outside of a sequence. If you need to express a similar condition within a sequence, you might need to reformulate it using other temporal operators.
Here’s an example that captures the essence of your original property using “throughout”:
In this example, I’ve replaced the “until” operator with “throughout,” which is allowed within a sequence context. This sequence asserts that when sig1 is 0, then for the next 7 time units, sig2 remains stable (does not change) until sig1 changes.
If the specific behavior you are trying to capture requires the “until” operator, you may need to express it in a property outside of a sequence or adjust the formulation to use other temporal operators that are allowed within a sequence context.