Hi, Following property shows elab issue: Property operator usage is not allowed in sequence context. What is wrong with it? How should it be written to resolve elab issue? (sig1==0) |-> ##7 (($stable(sig2)) until (sig1 [->1])); When I replace “until” with “throughout” it doesn’t show any issue. …

In reply to abhiraj171 : Try property ab; @(posedge clk) (sig1==0) ##7 1 |-> (($stable(sig2)) until (sig1 [->1])); endproperty

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Property operator in sequence context #SVA

SystemVerilog

abhiraj171 November 10, 2023, 3:31pm 6

In reply to MICRO_91:

The intent is to check after 7 clk cycles.