Problem with randc

SystemVerilog
,
1

Hello, first post of a beginning programmer here :)

I have an issue understanding how randc works. Below is a snippet of my sample code. From my understanding i should receive a full set of numbers between 0 and 13. Instead i got 0 twice, but no 11. What am i doing wrong?


randc bit [3:0] randomizer;
constraint 0_13 {randomizer inside {[0:13]};}

...

repeat 14
begin
randomize(randomizer);
$display("%d",randomizer);
end
2

In reply to Azmo:

I cannot repeat your results. Please show an MCVE, like this:

module top;
class A;
randc bit [3:0] randomizer;
constraint a_13 {randomizer inside {[0:13]};}
function void run;
   repeat (14)
     begin
	randomize(randomizer);
	$display("%d",randomizer);
     end
   endfunction
endclass

   A a=new;
   initial a.run; 
endmodule
3

Well… it is a bit of a mess. I am actually writing a test for an UVM project and I really should have mentioned it (and put it into the other forum section) from the beginning.

I already did a workaround by creating a static array containing all numbers between 0 and 13 and reshuffling it in place of using randc. Next time I run into randc I would give it more thought, but right now my plate is full with lots of other issues.

Thanks for the quick replay though!