Problem synchronizing always block

SystemVerilog
,
1

Hi all,

I have a problem with the time-step of an always block. Here is my issue.

I wanted to change a clock based on a signal going high. So I have the following :



initial begin
    fake_clk = 0;
end

always begin
    fake_clk = gen_fake_clk ? ~fake_clk : 1'b0;
    #((500000.0/freq)* 1us);
end

So, the fake_clk remains 0 until the gen_fake_clk goes high.

Now, I want to issue the fake_clk at the positive edge of the original clock (to make a nice transition instead of glitches). So the code to generate the gen_fake_clk pulse is as follows :


always @(induce_fake_clk) begin
    @(posedge original_clk)
        gen_fake_clk = 1'b1;
end

So, with this I wanted to generate a fake clock once I make the induce_fake_clk = 1’b1 from my testcase. This should start toggling from the positive edge of the original clock.

But, with this code, once I make the induce_fake_clk = 1’b1, the gen_fake_clk goes to 1’b1 but the fake clock doesn’t immediately start toggling. However, it remains 1’b0 for sometime (before the always block could the positive edge of gen_fake_clk).

in short I expect the following :

original clock       : |-----||-----||-----||-----|___|-----
induce_fake_clk  : ____________|--------------------------------------------
gen_fake_clk       : _________________|-----------------------------------------
fake_clk               : _____|--------||-------||------

But I observe the following :

original clock       : |-----||-----||-----||-----|___|-----
induce_fake_clk  : ____________|--------------------------------------------
gen_fake_clk       : _________________|-----------------------------------------
fake_clk               : _|--------||-------||------

So I’m wondering if there is a way to fix this issue? Any help appreciated

Thanks

2

In reply to szy0014:

If you just need to synchronize starting the fake_clk, you can replace all of your code with

initial 
    @(posedge original_clk iff induce_fake_clk)
    forever begin
       fake_clk = ~fake_clk;
       #((500000.0/freq)* 1us);
    end