Problem in using shift operator

SystemVerilog
1

I encountered a problem in using the shift operator. In the example below, ser_data is one bit wide and data_reg, input_data, temp_reg are 60 bits wide. This is an example of serializing data. Data is first read in data_reg. It is then shifted and sent out via ser_data.


// Read data @ encoder clock
always_ff @(posedge clk_en) 
	begin
	if (reset_n)
		data_reg <= input_data;
	end

// Write data to output @ 60*encoder clock
always_ff @(clk_ser) 
	begin
	if (reset_n)
	    begin
	    ser_data <= data_reg[59]; 
	    data_reg <= data_reg<< 1; // **THIS DOESN’T WORK: data_reg is always 0.**
	    end
	end

For debugging purposes, I used: temp_reg <= data_reg <<1
Now I can see the shifted data in temp_reg. Why doesn’t “data_reg <= data_reg<< 1” work ?

2

You are making assignments to data_reg in two different always_ff blocks. Perhaps you have a race condition.

3

Dave,
Actually, 1800-2009 section 9.2.2.4 Sequential logic always_ff procedure says

"Variables on the left-hand side of assignments within an always_ff procedure,
including variables from the contents of a called function, shall not be written to by any other process.

Thus, the
“data_reg <= data_reg<< 1; // THIS DOESN’T WORK: data_reg is always 0.” is illegal.

Ben Cohen, Design and verification expert (310) 997-2187
http://www.systemverilog.us/ ben@systemverilog.us

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4

In reply to ben@SystemVerilog.us:

@ben, dave - thank you