Printing hdl path in logfile

SystemVerilog
,
1

Hi,
How do I print the hdl paths in the logfile. I am using OVM methodology and VCS for running the simulation.
Any pointers in this regard would be appreciated.
Thanks,
Anshu

2

There is a %m format specifier in Systemverilog that prints entire hierarchy.

For example, in your HDL module, yuo can have the following for debugging purpose:


module abc();
initial begin
$display("I am here: %m"); // will print path till this module including this module instance name
end 
endmodule

If you want to print the class hierarchy, then there is a get_full_name() API in OVM.