Printing detailed UVM testbench toplogy

UVM
1

Hi,

Is there a way to print a UVM TB topology is much detailed way than the already present “print_topology”?

My intent is to display (a) all components instantiated (b) TLM port connections between components for starters.

Thanks

2

(a) Assuming all the components are created through the factory, you can use factory.print() which returns information about the classes registered with the factory and any overrides. There are also debug_create_by_type and debug_create_by_name
(b) For TLM ports you can use get_connected_to (port’s fanout network) and get_provided_to (port’s fanin network)

The following uvm cookbook section has more detailed information Builtin Debug