Predict() returns UVM_NOT_OK

Hi All,

I’m modeling a read only register, I faced a behavior of predict() function I couldn’t understand as following:

I call predict function:


The above assume failed it means the returned status is UVM_NOT_OK, but when I checked predict() uvm 1.2 code I noticed that when status is UVM_NOT_OK
I should get the following warning in my report but I have 0 warnings in my simulation, any idea please?

         if (m_parent.is_busy()) begin
           `uvm_warning("RegModel", {"Trying to predict value of field '",
              get_name(),"' while register '",m_parent.get_full_name(),
              "' is being accessed"})
           rw.status = UVM_NOT_OK;


In reply to Mohamed_TN:

  //The above assume failed it means the returned status is UVM_NOT_OK

I think above assertion get fail when status = UVM_IS_OK.
Because, as per below code of library. predict returns 1 for UVM_IS_OK.

  predict = (rw.status == UVM_NOT_OK) ? 0 : 1; // line  1949 uvm_reg.svh

So, when it returns UVM_IS_OK (1) your assertion will fail. right ? ( like below example )

module m;
  function int x(int i);
    x = i;
  endfunction : x
  initial begin
    for(int i=0;i<2;i++) assert(!x(i)) $display("Pass:-%0d",i); 
                                  else $error  ("Fail:-%0d",i);
endmodule : m

//Result :- 
# vsim -voptargs=+acc=npr
# run -all
# Pass:-0
# ** Error: Fail:-1
#    Time: 0 ns  Scope: m File: Line: 11
# exit

So as per my view, if your assertion is failing which is due to UVM_OK.
Hence, warning print for UVM_NOT_OK is not coming.

So,i think you need to change your code to below

  assert(regmodel.regA.fld1.predict(1)); // So, it will give error for UVM_NOT_OK


In reply to harsh pandya:

I misunderstood the use of assert in this context, thanks a lot for the example which illustrate the issue.