Precision Loss in Shifting

SystemVerilog
,
1

Let’s say I am shifting left a smaller size logic, then assigning it to a bigger logic. How the RHS execution is evaluated? I have a simple example below. Is shifting happening on RHS logic size ( = 4 bits) or LHS logic size ( = 8 bits)? Will I lose any MSB bits in ‘a’?


module my_module (
    input logic [3:0] a,
    input logic [1:0] shift_amount,
    output logic [7:0] b
)
assign b = a << shift_amount;

endmodule
2

In reply to veli:

You could have created a simple example to test your assumptions.

module top;
  
  logic [3:0] a ='1;
  logic [1:0] shift_amount = '1;
  logic [7:0] b;

  initial begin
    b = a << shift_amount;
    $displayb(b);
  end
endmodule
3

In reply to dave_59:

Thank you @dave_59. For further readers, I run the code below in “Modelsim SE-64 2019.1”:


logic [3:0] a            = 'b1111;
logic [1:0] shift_amount = 'd3;
logic [7:0] b            = 'd0;
     
  initial begin
    $displayb("Before shift, b: %8b \n", b);
    b = a << shift_amount;
    $displayb("After shift,  b: %8b \n", b);
  end

I got the terminal output below:

Before shift, b: 00000000

After shift, b: 01111000

Thus, I had no precision loss in a.