I am trying to port an existing verilog testbench to UVM testbench, trying to avoid as much recoding as possible. I have a legacy testbench verilog module, which instantiates some other verilog modules, and also has continuous assign statements and procedural code inside ‘initial’ and ‘always’ blocks. It also has tasks/functions. I found an article on how to wrap the existing verilog code inside a class, in the Verification Horizon publication of Nov 2010; but the article only mentions on porting of tasks and functions. How do I port the verilog code inside the module which instantiates other modules, assign statements and procedural code inside ‘initial’ and ‘always’ blocks into class-based structure?
Here is the snippet of the verilog code:-
**module bfm_analog_top
#(
parameter NAME = “bfm__analog_top”,
…
)
(
input CLK,
inout LR_SDI,
…
);
wire clk_osc;
// Delay through Level Shifter: 2 x INVX1 ~ 0.2ns
assign #0.2 clk_ref = clk_osc;
// Delay through Level Shifter: 2 x INVX1 ~ 0.2ns
assign #0.2 clk_ext = CLK;
// Delay through Sigma-Delta ADC + Level Shifter: 2.5ns + 2 x INVX1 ~ 2.7ns
assign #2.7 clk_adc_p1 = ana_blk_ena_0[4] ? clk_adc : 1’b0;
//Module instantiation
tristate_buf tristate_buf_SDO_inst (
.oe(sdo_oe),
.ie(sdo_ie),
…
);
assign (weak1, weak0) SDO = 1’bz; //always z no matter what sdo_amo_ena
wire [ADC_OUT_WL-1:0] bfm_adc_sample;
always @(negedge clk_adc) //@clock
begin
#1 adc_out <= bfm_adc_sample;
end
always @(osc_dis) //@event
begin
if(osc_dis == 0)
bfm_clk_osc_inst.start();
else
bfm_clk_osc_inst.stop(0);
end
// FIXME: add more signals?
initial
begin
adc_out = 0;
#10
$fmonitor(log_file, "%t %s.bias_trim: %h", $realtime, NAME, bias_trim);
....
init(); //calling task
end
…
…
endmodule
**