Port size does not match connection size- Modelsim

SystemVerilog
,
1

I have the following systemverilog file and testbench and I’m getting the size not matching for m variable Y_m and I’m no able to figure out why? Any help would be appreciated. Thanks!
File:

module sign_mag(
input logic [3:0]A_m,B_m,
input logic A_s,B_s,op,
output logic Y_s,
output logic [3:0]Y_m
);
always_comb
begin
if(op==1) //addition
begin
if((A_s==0&&B_s==0)|(A_s==1&&B_s==1))
begin
assign Y_m=A_m+B_m;
assign Y_s=A_s;
end

//comparator c_1(A_m,B_m,comp);
if(A_m>B_m)
begin
assign Y_m=A_m-B_m;
assign Y_s=A_s;
end

if(A_m<B_m)
begin
assign Y_m=A_m+B_m;
assign Y_s=B_s;
end
end

if(op==0) //subtraction
begin
if((A_s==0&&B_s==0)||(A_s==1&&B_s==1))
begin
if(A_m>B_m)
begin
assign Y_m=A_m-B_m;
assign Y_s=A_s;
end
if(A_m<B_m)
begin
assign Y_m=B_m-A_m;
assign Y_s=B_s;
end
end
else 
begin
assign Y_m=A_m+B_m;
if(A_m>B_m)
begin
assign Y_s=A_s;
end
if(A_m<B_m)
begin
assign Y_s=B_s;
end
end
end
end
endmodule

testbench:

module testbench_LAB_2();
logic a_s,b_s,op;
logic [3:0]a_m,b_m;
logic y_s;
sign_mag dut(a_s,a_m,b_s,b_m,op,y_s,y_m);
initial
begin
a_s=1; a_m=3; b_s=0; b_m=2; op=1; #10;
a_s=1; a_m=3; b_s=1; b_m=2; op=1; #10;
a_s=0; a_m=3; b_s=0; b_m=2; op=1; #10;
a_s=1; a_m=3; b_s=0; b_m=2; op=0; #10;
a_s=1; a_m=3; b_s=1; b_m=2; op=0; #10;
end
endmodule
2

In reply to VIKRANT97:

You have no wire y_m declared in the testbench, so it is creating an implicit wire which is one bit wide.

3

In reply to cgales:

Thank you!