I have some experience in Verilog (6 months) and C++ (2 years) and now want to go for system Verilog.So Please let me know any good book/weblink for system verilog.
In reply to lovelyece:
Stuart Sutherland wrote many good books on SystemVerilog, see
He also wrote many excellent papers, see
On assertions, you may want to consider my book SystemVerilog Assertions Handbook, 3rd Edition, 2013that demonstrates many simulatable models for the application of assertions.
Assertions have been proven to be very beneficial in pinning down (and clarifying) requirements, and in the debug process.
Ben Cohen http://www.systemverilog.us/
- SystemVerilog Assertions Handbook, 3rd Edition, 2013
- A Pragmatic Approach to VMM Adoption
- Using PSL/SUGAR … 2nd Edition
- Real Chip Design and Verification
- Cmpt Design by Example
- VHDL books