CRC5=X^5+X^4+X^2+1
I HAVE WRITTEN CRC CODE FOR SERIAL BIT DATA IN FOLLOWING
I DIDNT GET TEST BENCH FOR SENDING 11110101
module crc5(data,clear, clk,out);
input data,clk,clear;
output [4:0]out;
reg[4:0]out;
wire lfsr;
assign lfsr= data^ out[4];
always @(posedge clk or posedge clear)
begin
if (clear)
begin
out = 0;
end
else begin
out[4] = out[3];
out[3] = out[2] ^ lfsr;
out[2] = out[1];
out[1] = out[0] ^ lfsr;
out[0] = lfsr;
end
end
endmodule
PLEASE HELP ME!!!
In reply to ajit sinam:
You need to first clarify your verification requirements, and once you understand them, specify the verification environment (the approach), and then the coding is the simplest thing. Specifically, for this small example, what are your goals? For example,
In your design and verification environment, consider using SystemVerilog instead of Verilog.
Consider using the SystemVerilog randomize function for driving the stimulus vectors. Also consider using SystemVerilog assertions in the verification.
From my extensive experience with forums, you get responses for generic types of questions related to language use, or usage of an approach, or a problem that is weird. You do not get answers in doing code for you, or try to debug your code. Anyway, an advice.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us