Please explain steps involved in verification of a processor?

SystemVerilog
,
1

Hai, I have designed lc3 microcontroller using system verilog. I want to verify my DUT by developing constraint random coverage driven reusable verification environment. I know developing environment for simple DUT like adder.but processor involves instruction memory(text file) and data memory( which is just a register file in my RTL code).Is it correct way of designing? if Yes, how to communicate with memory in scoreboard?

2

In reply to durgabhavani chunduru:

I have designed lc3 microcontroller using system verilog. I want to verify my DUT by developing constraint random coverage driven reusable verification environment. I know developing environment for simple DUT like adder.but processor involves instruction memory(text file) and data memory( which is just a register file in my RTL code).Is it correct way of designing? if Yes, how to communicate with memory in scoreboard?

Since no one answered yet, I’ll take a stab at it.

  1. As you stated, devices external to the LC3 processor are considered as BFMs, and are modeled as such. Thus, memories are modeled as arrays.
  2. Those memories are part of the testbench, at the top level module. The preferred approach in UVM is to use interfaces, thus you could tie the DUT signals to those interfaces. You can also instantiate, or model the memories inside the interfaces; actually, not a bad idea.
  3. There are papers available on LC3. I found this one interesting
    ece 745 : asic verification project 1 lc-3 design spec
  4. Aside from suggestions in the above paper on verifying LC3, I strongly recommend the use of assertions on the interfaces, and also on the design itself using SystemVerilog checkers that can be bound to the dut.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

  • SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
  • Component Design by Example ", 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
  • VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115