Placing Begin End for Constrianed if else

SystemVerilog
, ,
1

Hello Everyone,
I want to place a begin end for the if and else-if condition so that I can give a ucm_info print statement. Following is the piece of original code:

  if (!rw_txn.randomize() with { if (cfg.controller.if_type inside {A, B,C})
     rw_txn.tgt_id   == m_seq_cfg.Target_ID; 
   else if (cfg.srcID == 0)
     rw_txn.tgt_id   == m_seq_cfg.Target_ID;

Following is my intention

 if (!rw_txn.randomize() with { if (cfg.controller.if_type inside {A, B,C}) begin
    `uvm_info("","Display_19",UVM_NONE);
     rw_txn.tgt_id   == m_seq_cfg.Target_ID; 
   end
   else if (cfg.srcID == 0) begin//TgtID is fixed in HNF seq when multiple_srcID=0
    `uvm_info("","Display_20",UVM_NONE);
     rw_txn.tgt_id   == m_seq_cfg.Target_ID; 
   end

With this approach I get error which says:
near “begin”: syntax error, unexpected begin

How can I include a begin end in this constrained if else. Any help or hint would be appreciable.
Thanks

2

In reply to kritikagoell:

Constraints are not procedural code, they are boolean equations. You cannot put procedural. statements inside them (`uvm_info is a macro that inserts a lot of procedural code, eventually calling $display).

if (A) B else C;

is a shortcut for the following expression

(!A || B) && (A || C)

You’ll have to put another if statement after the call to randomize() to print your messages.